1. Field of the Invention
The invention relates to the formation of interpoly dielectric in flash and other floating-gate-based memory, and more particularly to the use of an in-situ steam generation (ISSG) procedure in the formation of a first oxide layer.
2. Description of Related Art
Read only memory (ROM) is a memory device that contains fixed data patterns determined at the time of fabrication. In the fabrication of a ROM, it is necessary to make a storage cell that maintains data after the applied power is turned off. Because data to be stored in a ROM is predetermined prior to fabrication, the change of a single bit in the stored data would require an alteration of the entire circuit and the manufacturing process.
To avoid having to custom design each ROM from scratch, ROMs are often manufactured using a process known as mask programming, by which data is stored in the ROM at one of the final process steps. A ROM made this way is called a mask ROM because the programming in the device is carried out by means of the mask at one of the final process steps, typically a metal layer.
Although mask ROM is more flexible than conventional ROMs, data must still be stored in the device during fabrication. In this regard, programmable read only memory (PROM) is a further improvement to the mask ROM. Data can be electrically programmed in a PROM device by the user. However, a PROM cell can be programmed only once.
A still further improvement to mask ROM and PROM is an EPROM, or erasable programmable ROM. A typical EPROM is shown in FIG. 1A, where a floating gate 12 is located between a control gate 14 and a substrate 10. An isolation region 16 surrounds both the floating gate 12 and the control gate 14. The isolation region includes a bottom oxide layer 110 between the floating gate 12 and the substrate 10, and a gate oxide layer 112 between the floating gate 12 and the control gate 14. Note that an EPROM cell is structurally similar to an NMOS device, except that the former has two gate conductors and no LDD (lightly doped drain) region.
The contacts of the source 13 and the substrate 10 of an EPROM are both coupled to ground, whereas the control gate 14 and the contact of the drain 15 are connected to high potentials VG and VD, respectively. The control gate 14 is reverse-biased with respect to the drain 15. Because the drain 15 is not protected by an LDD structure, the PN junction of an n-doped drain 15 and a p-doped substrate 10 will foster the well-known carrier multiplication effect. Some of the hot electrons produced as a result of this effect will be collected by the drain 15, while the rest of them will transverse through the isolation region 16 and be trapped in the floating gate 12. The voltage supplied to the control gate 14 and the drain 15 are switched off as soon as these hot electrons are trapped in the floating gate 12. The electrons trapped in the floating gate do not have enough energy to escape because of the potential barrier in the isolation region 16 surrounding the floating gate 12. As a consequence, the data may be stored in the floating gate 12 for years.
The electric charges in the floating gate 12 determine the value stored in the memory cell. If no electric charge is stored at the floating gate 12, the floating gate 12 will have no influence on the electrical field that control gate 14 generates in the channel region between the source 13 and drain 15. However, if the floating gate 12 is charged with electrons, the electric charges in the floating gate 12 will shield the field of the control gate 14 and generate an electrical field in the channel region; this second electrical field is opposite in sign to the field of the active control gate 14. Thus, a small active signal at the control gate 14 cannot generate a sufficiently strong field to turn on the transistor. Only with a much higher control gate potential can the storage transistor be turned on; i.e., the field of the control gate 14 must be strong enough to compensate the field of the floating gate 12 and to make the channel between source 13 and drain 15 conductive.
Referring again to FIG. 1A, an EPROM can be programmed by loading the floating gate 12 with electrons. The stored data may be erased by exposure to ultraviolet (UV) radiation for a certain period of time. Essentially, the electrons trapped in the floating gate 12 absorb sufficient energy from the UV light and escape from the floating gate 12 in the same way as they were previously trapped. An EPROM with an empty floating gate 12 may be reprogrammed again in accordance with the above-described programming process.
Because the electric charges in the EPROM can only be erased with ultraviolet radiation, it is necessary for the packaging of an EPROM to have a window made of, e.g., quartz glass, to allow the die to be exposed to ultraviolet radiation. This results in an increase in the manufacturing cost. Furthermore, all the electric charges (and hence any data or program) in the device are erased all at once, dictating a time-consuming reprogramming process. These concerns can be overcome by using an electrically erasable programmable read-only memory (EEPROM), where the electric charges in the floating gate 12 can be electrically erased. As shown in FIG. 1B, EEPROM is programmed in the same way as the EPROM, i.e., through hot electron ejection generated by a relatively long voltage pulse between the control gate 14 and the drain 15. In this process, electrons generated in the drain 15 traverse through an oxide layer 18 into the floating gate 12. This is the well-known Fowler-Nordheim tunneling mechanism, and the bottom oxide layer 18 is known as tunneling oxide layer. In the case where both the floating gate 12 and the control gate 14 are made of polysilicon, the gate oxide layer 112 is sometimes called an interpoly dielectric. The interpoly dielectric need not be strictly an oxide; often it is made of an oxide-nitride-oxide (ONO) composite.
To erase an EEPROM, an inverse voltage is applied between the control gate 14 and the drain 15. As a result, electrons in the floating gate 12 travel to the drain 15 again through the tunneling oxide layer 18. The stored data is erased accordingly; new data can be programmed into the memory cell again. Because the inverse voltage is applied to each pair of the control gate 14 and the drain 15, each gate can be erased independent of other gates. This allows bit-by-bit erasure and reprogramming of the EEPROM cell, a significant improvement over the aforementioned EPROM cell.
A more recent type of memory cell is the flash EPROM cell, which is often used as a substitute for floppy disk or hard disk drives. This is because flash memory may be programmed as flexibly as a random access memory (RAM). The structure of flash memory cells is similar to that of EEPROMs, except that the tunneling oxide layer 18 is often made thinner than that in an EEPROM memory cell, allowing lower programming and erasure voltages applied between the control gate 14 and the drain 15; see FIG. 1A. Flash memories also typically have simplified array structures, improving speed and density but permitting erasure only in a block-by-block manner.
Many varieties of floating gate memories have been developed in addition to those described above, including twin bit or split cell memories, memories which use conductive material (e.g. polysilicon) as the floating gate, and memories which use dielectric material (e.g. silicon nitride within an ONO composite) as the floating gate.
Data storage in all these variations is accomplished by trapping hot electrons or Fowler-Nordheim tunneling electrons in a floating gate. Therefore, it is vitally important to control the thickness of the gate dielectric layer and the tunneling oxide layer between the floating gate and the semiconductor substrate.
Typical conventional methods for controlling the thickness of the gate oxide or tunneling oxide layer are depicted as follows. As shown in FIG. 2A, after a floating gate 12 is fabricated, an interpoly dielectric layer is formed on the floating gate 12. This interpoly dielectric layer is a composite of oxide-nitride-oxide (ONO) dielectric materials, including a bottom silicon oxide layer 22, a silicon nitride layer 24, and a top silicon oxide layer 26; all three layers are deposited typically via a chemical vapor deposition (CVD) process. The conventional bottom oxide layer 22 is usually grown to a thickness between 20 to 40 nm; the nitride layer 24 may be anywhere between 10 to 25 nm; and the top oxide layer 26 is usually limited to approximately 3 to 4 nm.
Because a gate oxide layer must be grown in the peripheral area after forming the oxide-nitride-oxide composite structure, the interpoly dielectric layer in the peripheral area must be removed before the oxidizing process. Since it is difficult to grow a gate oxide layer on the silicon nitride layer 24, the conventional process dictates that certain portions of the silicon nitride layer 24 of the ONO interpoly dielectric in the peripheral area be completely removed before growing the gate oxide. Several conventional methods may be used to accomplish this goal.
One method for removing selected portions of the ONO dielectric is shown in FIG. 2B, where the top oxide layer 26 and the silicon nitride layer 24 over a gate oxide growth region 28 are removed via a dry etch process using CF4 as the etchant. Because the etch rate in the bottom oxide is relatively low, the dry etch process stops within the bottom oxide layer 22. Next, a gate oxide layer 30 is formed on the bottom oxide layer 22 through a thermal oxidation process; see FIG. 2C. The thickness of the remaining bottom oxide layer 22 is an important factor in this method. If the thickness of the remaining bottom oxide layer 22 cannot be ascertained, it will be difficult to control the thickness of the gate oxide layer that is subsequently grown. On the other hand, it is not advisable to etch away all of the remaining bottom oxide 22 with hydrofluoric acid, because the photoresist film 32 (shown in FIG. 2B) cannot be used as a shield to the hydrofluoric acid; the ONO structure on top of the floating gate 21 will also be etched. Using the buffered oxide etch (BOE) process does not solve this problem, either, because the field oxide region 34 will be etched at a greater etch rate, causing deterioration of the isolation region between the gates.
A second method for removing selected portions of the ONO dielectric is depicted in FIG. 2D, in which a dry etch process (using CF4 as the etchant) is used to remove the entire ONO structure from the gate oxide growth region 28. This etch process stops at the substrate 10. Next, as is illustrated in FIG. 2E, a gate oxide layer 36 is formed on the gate oxide growing region 28 via a thermal oxidation process. This method requires that the dry etchants be able to etch silicon dioxide but not silicon; otherwise, the silicon substrate would also be etched, resulting in adverse effects such as gate oxide quality degradation.
In U.S. Pat. No. 6,136,647, ONO was used as the interpoly dielectric layer in a floating gate memory structure. But in order to facilitate removal of the nitride sub-layer before growing the gate oxide, the interpoly dielectric was formed initially to include only an oxide-nitride (ON) composite layer instead of the full ONO layer. The portion of the ON layer over the gate oxide growth region was then removed. The removal of such an ON film was said to cause much less damage to the substrate compared to the conventional case of the ONO film. After the removal process, a thermal oxidation process and an oxide CVD process were used to grow the gate oxide and the top oxide of the ONO layer simultaneously. This process was said to provide better assurance of the quality of the gate oxide and the ONO interpoly dielectric layers.
However, thermal oxidation processes and oxide CVD processes can sometimes create significant stresses within the oxide layer. The large stresses often create defects in nearby active regions, which can result in leakage current and degrade reliability. The insulation between the two gates can degrade, and word-line to word-line shorts can occur.
Accordingly, it is an object of the present invention to provide a method for fabricating a memory device that avoids the drawbacks of the conventional methods.